1. Field of the Invention
The present invention relates to a multiple-chip semiconductor device in which the same package envelops a semiconductor power chip, viz., a power transistor or a power MOSFET, and a control semiconductor chip for controlling the semiconductor power chip. The invention also relates to a method of manufacturing such a multiple-chip semiconductor device.
2. Description of the Background Art
FIGS. 1 and 2 are a plan view and a cross sectional view of a conventional multiple-chip semiconductor device, respectively. The conventional multiple-chip semiconductor device is manufactured in the following manner.
A first step of fabrication is, as shown in FIG. 1, preparation of a leadframe 5 which consists of a tiebar 1 and external leads 2 to 4 extending from the tiebar 1. Of the external leads 2 to 4, the external leads 2 and 3 respectively have at their ends mounting areas 2a and 3a which respectively mount a semiconductor power chip 6 (hereinafter "power chip") and a control semiconductor chip 7 (hereinafter "control chip") which controls the power chip 6.
The power chip 6 and the control chip 7 are then attached on the mounting areas 2a and 3a. This is followed by wiring for electrically interconnecting the external leads 2 to 4, the power chip 6 and the control chip 7 with aluminum wires 8 and gold wires 9 and subsequent transfer molding for forming a monolithic resin package 10 (FIG. 1 ). The external leads 2 to 4 are then severed from the tiebar 1, completing the multiple-chip semiconductor device of FIG. 2. In FIGS. 1 and 2, indicated at reference numeral 11 is a through hole.
Due to the presence of the power chip 6, how to efficiently radiate heat which is developed by the power chip 6 is an important consideration in designing the multiple-chip semiconductor device described as above. To ensure efficient heat dissipation, the leadframe 5 is customarily made of metal which has a relatively high heat conductivity, typically copper, and finished relatively thick.
The package pin counts and the chip-feature size will undoubtedly continue to increase with improvement in capabilities of the control chip 7. Hence, to satisfy the demand, it is necessary, that the leadframe 5, made of copper, is designed in tine configuration. However, the thicker the leadframe 5 the more difficult it becomes to form the leadframe 5 in fine configuration.
On the other hand, with a decrease in the leadframe thickness for easiness in fine processing, efficiency of heat radiation decreases. For multiple-chip semiconductor devices in which a thin leadframe 5 is used, serious problems arise due to heat produced in the power chip 6; the semiconductor devices will fail, or will be destructed.
The problem above is joined by another inconvenience. As described earlier two wire bonding steps, one using the aluminum wires 8 and the other using the gold wires 9, are required to fabricate the conventional multiple-chip semiconductor device. The aluminum wires 8 are used for interconnection of the power chip 6. This is because the power chip 6 is a semiconductor element which handles large power and aluminum endures large power. The gold wires 9 are used for interconnection of the control chip 7 since interconnecting using aluminum wires is not suitable for a small and delicate chip like the control chip 7. Hence, the two wire bondings need to be performed separately and serially. A result of this is a lowered manufacturing efficiency and a prolonged manufacturing time.